1. Field of the Invention
The present invention generally relates to controlling the amount of gate wrap-around within metal oxide semiconductor field effect transistors by adjusting the depth of divots within the shallow trench isolation regions adjacent the gates.
2. Description of the Related Art
It is well recognized that divots in shallow trench isolation (STI) regions adjacent transistor wells, which are a consequence of removing the sacrificial oxide layers in surface-channel N-type metal oxide semiconductor field effect transistors (NFET's), are responsible for causing the gate conductor to "wraparound" the silicon corners in NFET's which results in poor threshold voltage (Vt) controllability of the NFETs. Such divots 12, 13 are shown adjacent a buried-channel PFET device in FIG. 1. Because of this poor threshold voltage controllability, the doping concentration within the P-well beneath the gate conductor is increased in order to meet the target off-current (e.g., the drain-source current where the field effect transistor is off--"Ioff").
However, a problem exists with this conventional solution of increasing the doping concentration because a drastically increased array junction leakage has been observed with increased P-well surface concentration (e.g., a surface concentration greater than 5.times.10.sup.17 cm.sup.-3). Because of this array NFET problem arising from the STI divot, there has been great interest in minimizing divot depth.
The invention minimizes divot depth for NFET devices and at the same time avoids causing problems with other devices manufactured on the same wafer, such as buried-channel PFET devices.